1. Field of the Invention
The invention relates to a clock and data recovery circuit, and more particularly to a multi-band burst-mode clock and data recovery circuit.
2. Description of the Related Art
Passive optical networks (PONs) solve bottlenecks among back-bone networks and LANs. To connect many optical network units (ONUs) with an optical line termination (OLT), the time division multiple access (TDMA) scheme is adopted. Therefore, the OLT may receive the sequent burst-mode data from ONUs. The clock and data recovery (CDR) circuit at the OLT must detect the input data within tens of bit times and recover the clock and data. It is difficult for the conventional CDR circuits to settle within such a short time. Conventional gated voltage-controlled oscillators (GVCOs) are roughly classified into two categories. One uses the edge detection circuit with a half bit-time delay line to trigger the GVCO. The accuracy of the half bit-time delay line limits the jitter tolerance and bit-error rate. The other combines two GVCOs with a NOR gate or multiplexer to realize a burst-mode clock and data recovery (BMCDR) circuit. The conventional GVCOs operate within two states: one is the oscillating state and the other is the latching state. The result is significant inter-symbol interference (ISI) caused by random data patterns for the GVCOs. Moreover, the delay cells in a GVCO are composed of logic gates instead of simple inverters, which increase the bandwidth requirement of the delay cells. In the disclosure, a half-rate GVCO using only multiplexers is presented. The bandwidth requirement of the delay cells is relaxed and low ISI is also achieved. Furthermore, a novel multi-band BMCDR architecture combined with proposed circuits is as well to meet the different standards specified by PONs.